Semiconductor device manufacturers often perform systematic tests to determine whether or not the semiconductor devices that they manufacture satisfy certain design parameters. The tests performed may include, for example, device parameter tests (DC testing), device logic function tests and/or device timing tests (AC testing). The semiconductor device being tested is sometimes called the Device Under Test or “DUT.” The test system used to perform the tests on the DUT is often referred to as Automatic Test Equipment or “ATE.”
Typically, the ATE is controlled by a computer that may provide voltage, current, timing, functional status and/or other information to and from the DUT. The computer may also execute a test program that monitors the response of the DUT to the respective tests. The results of the tests may, for example, be compared with predetermined thresholds to make decisions as to whether or not the DUT passed or failed a test at issue. The ATE may include, for example, a power supply, a counter, a signal generator, and a pattern generator. A Pin Electronics or “PE” circuit may be used as an interface between the ATE and the DUT to provide input signals to the DUT and receive output signals from the DUT. For example, during a device parameter test, the PE circuit might apply an input voltage to the DUT and receive an output current from the DUT, or might apply an input current to the DUT and receive an output voltage from the DUT.
A semiconductor test device is disclosed in International Patent Publication No. WO 2003/052767. This test device may be used to test a plurality of semiconductor devices simultaneously. The test device may input the same test data pattern waveform to the same pin of a plurality of semiconductor devices to perform the testing.
FIG. 1 is a schematic of a conventional semiconductor test device that may be used to test a semiconductor memory device. The memory device may comprise, for example, a dynamic random access memory device (“DRAM”). As shown in FIG. 1, the device may include a clock signal generator 10 for generating a timing clock signal CLK. The device further includes a pattern generator 12, such as an algorithmic pattern generator, that transmits a clock signal generation start signal T1 to the clock signal generator 10, receives the clock signal CLK from the clock signal generator 10 and generates an address pattern, a data pattern, and/or a control pattern. The device further includes a pattern data selector 14 that allocates channels to the address pattern, the data pattern and/or the control pattern that are received from the pattern generator 12. A signal generator 16 such as a timing generator format controller may be provided that generates the actual test data in synchronization with the timing clock signal CLK based on the pattern data output from the pattern data selector 14. A buffer driver 18 is provided that generates a buffer driving signal, and a plurality of buffers 20 are used to buffer the test data generated by the signal generator 16. A plurality of switches 22 are provided that switch the data output from the plurality of buffers 22 to the DUT 30.
FIGS. 2 and 3 are exemplary diagrams of a conventional test pattern. In particular, FIG. 2 shows an Xmarch CL4 pattern, and FIG. 3 shows an Xmarch CL5 pattern. In FIGS. 2 and 3, AWRA refers to an “active read command”, and LAL is a “second command.” FIG. 4 is a timing diagram illustrating the generation of timing clock signals according to the conventional Xmarch CL4 pattern of FIG. 2.
Aspects of the present invention relate to semiconductor memory devices that use Column Address Strobe or “CAS” techniques. As will be understood by persons of skill in the art, CAS latency involves the period of time (or number of clock cycles) that must pass before the data that is output in a read operation appears on the output pins. As used herein, the term “CAS latency number” refers to the number of clock cycles of a clock signal that is synchronized with an external command that must pass after application of a read or write command before the input/output data can be presumed valid.
Operations for outputting test pattern data using the conventional test device of FIG. 1 will now be described with reference FIGS. 1-4. Operations may begin with the clock signal generator 10 receiving a clock signal generation start signal T1 from the pattern generator 12. The clock signal generator 10 generates a timing clock signal CLK in response to the start signal T1. The pattern generator 12 receives the clock signal CLK from the clock signal generator 10 and generates a test pattern that comprises an address pattern, a data pattern and a control pattern. These patterns are output to the pattern data selector 14. The test pattern may be designed, for example, to generate commands to read or write data to/from the DUT after four or five cycles of a clock signal. In particular, the test pattern may be generated according to the CAS latency number. The pattern data selector 14 allocates channels to the address pattern, the data pattern and the control pattern and outputs the channel-allocated patterns to the signal generator 16. The signal generator 16 generates actual test data based on the pattern data allocated by the pattern data selector 14 in synchronization with the timing clock signal CLK, and outputs the generated data to the respective buffers 20. The buffer driver 18 generates a buffer driving signal and applies it to the respective buffers 20. The plurality of buffers 20 buffer the actual test data according to the buffer driving signal output from the buffer driver 18 and apply the buffered data to the respective switches 22. The plurality of switches 22 switch on to output the data in the buffers 20 to the DUT 30.
Thus, the pattern generator 12 of the above-described conventional semiconductor test device generates a test pattern that has a CAS latency number that, for example, corresponds to the test pattern of FIG. 2 or 3, and the signal generator 16 generates actual test data based on the test pattern and transmits the generated test data to the DUT 30.
When the test pattern is formed with a four-cycle clock signal 4CLK as shown, for example, in FIG. 2, the conventional semiconductor test device generates an active read command for reading data after the generation of four cycles of the clock signal CLK (see FIG. 4). However, if the CAS latency number of the semiconductor device is changed, for example, from four to five, a whole new set of test patterns is required. Accordingly, an increase or decrease of one in the CAS latency number requires a doubling in the number of test patterns required. Larger increases (or decreases) in the CAS latency number require a corresponding increase in the number of test patterns to twice the change in the CAS latency number. As the number of test patterns increases, the likelihood human errors in programming and/or verification of the test patterns increases.